IEDM

09/03/2026

short courses are on Sunday, December 13, from 8:00 AM–5:00 PM.

Two full-day courses are available:

Short Course 1: Logic and System Innovations Powering the AI Era

∙ Distributed network design for AI: Evolution, scaling, and system Implications — Brad Beckmann, AMD
∙ Advanced logic transistor scaling and 3D architectures in the Angstrom era — Seung Hoon Sung, Intel
∙ Edge device performance/power enhancement in mobile SOC platform through device to DTCO to STCO — Jun Yuan, Qualcomm
∙ Atomic layer processing: Applications in advanced semiconductor devices — Thorsten Lill, Lam Research
∙ Reliability challenges in advanced packaging and system-level interaction — Yao-Chun Chuang, TSMC
∙ Cryogenic electronics for quantum computing — Loïc Le Guevel, Google

Short Course 2: Powering Next-Generation AI and HPC with Advanced Memory Technologies

∙ Memory-centric computing for the generative AI era — Damien Querlioz, CNRS
∙ HBM design and technology challenges for AI generation — HyunBae Lee, SK Hynix
∙ Oxide-semiconductor channel transistor DRAM (OCTRAM): High-density and low-power consumption DRAM technology for sub-10nm nodes and beyond — Keiji Ikeda, Kioxia
∙ The evolving role of NAND: Technology and system scaling from traditional storage to memory-storage convergence — Kishore Muchherla, Micron
∙ Spintronics for MRAM and beyond — Shunsuke Fukami, Tohoku University
∙ Chiplet and advanced packaging technologies for AI and HPC systems — John Knickerbocker, IBM

Short courses typically sell out. Register: ieee-iedm.org/attendee/registration-details

08/27/2026

tutorials are on Saturday, December 12, from 1:30–6:00 PM.

Six tutorials run across two parallel tracks.

Time slot 1 (1:30–2:50 PM):

Tutorial 1: Evolution of the transistor from planar to nanosheet and beyond — Larry Bair, AMD
Tutorial 2: Chiplet, heterogeneous integration, 3D stacking technologies principles and state of the art — Olivier Noblanc, ST Micro

Time slot 2 (3:05–4:25 PM):

Tutorial 3: Memory technologies and system co-optimization in the AI era: Past, Present, and Future — Fatih Hamzaoglu, Intel
Tutorial 4: Diverse memory technologies for adaptive computing: From device physics to cooperative architectures — Elisa Vianello, CEA-Leti

Time slot 3 (4:40–6:00 PM):

Tutorial 5: AI in physics-based semiconductor modeling: From PDE-constrained learning to agentic TCAD/DTCO workflows — Pratheep Balasingam, Synopsys
Tutorial 6: Advanced optical devices and wafer-scale assembly for next-generation CPO and optical I/O — Joris Vancampenhout, Imec

Tutorials typically sell out. Register: ieee-iedm.org/attendee/registration-details

08/20/2026

registration is open: ieee-iedm.org/attendee/registration-details

Early registration rates are available through November 10, 2026. Hotel reservations at the Hilton San Francisco Union Square close the same day.

Registration options include the full conference, short courses, and tutorials. All registrations include OnDemand access to recorded presentations from December 21, 2026.

Devices at the Heart of the Intelligence Revolution
Dec 12–16, 2026 | Hilton San Francisco Union Square

07/13/2026

40% of presentations at IEDM are delivered by students.

Papers submitted by students are considered for the Roger A. Haken Best Student Paper Award.
Travel and registration support is available (You can request it at the time of submission).

Submission deadline: July 16, 2026.
Full call for papers at https://ieee-iedm.org/call-for-papers/overview/

Theme: Devices at the Heart of the Intelligence Revolution
Dec 12–16, 2026 | Hilton San Francisco Union Square

07/06/2026

IEDM 2026 invites submissions across 9 technical areas. Check where your research fits.

Full call for papers: https://ieee-iedm.org/call-for-papers/overview/

Devices at the Heart of the Intelligence Revolution
Dec 12–16, 2026 | Hilton San Francisco Union Square

06/29/2026

IEDM 2026 is now accepting paper submissions across 9 technical areas.
Submission deadline: July 16, 2026.

Full call for papers at: https://ieee-iedm.org/call-for-papers/overview/

Theme: Devices at the Heart of the Intelligence Revolution
Dec 12–16, 2026 | Hilton San Francisco Union Square

03/31/2026

coverage by Australia's Mirage News with an article on the KAIST paper on "smart gate" NAND Flash technology: "KAIST Boosts Storage with Smart Gate Tech"

From smartphones to large-scale AI servers, most digital information in modern society is stored in NAND flash memory*. KAIST researchers have developed an innovative technology that can overcome the limitations of next-generation semiconductors, where more data must be stored in smaller spaces. This advancement is expected to serve as a key enabling technology for realizing ultra-high-capacity memory.

From smartphones to large-scale AI servers, most digital information in modern society is stored in NAND flash memory*. KAIST researchers have

03/26/2026

coverage in the UK's Semiconductor Today with an article describing imec's 2D p-FETs presented at IEDM: "Imec presents record WSe2-based 2D-pFETs for extending logic technology roadmap"

SemiconductorToday2026(01)Feb

01/07/2026

Registration for online access to technical content is open until January 31. Registered attendees will have access to OnDemand video content until March 31, 2026.

Registration link here:

You will be required to enter your email address that is associated with your IEEE membership, as well as your password. Registration Tip: Please clear your cache and/or open new incognito window before registering.