The division of Computer Engineering performs teaching and research on processor architectures and logic design.
13/03/2019
Another paper.
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC A direct digital-to-RF converter (DRFC) is presented in this work. Due to its digital-in-nature design, the DRFC benefits from technology scaling and …
06/02/2019
The paper "Optimium Circuits for Bit-Dimension Permutations" by Mario Garrido, Jesus Grajal, and Oscar Gustafsson was accepted to IEEE Transactions on VLSI Systems during the seasonal holidays and is now available as early access at
Optimum Circuits for Bit-Dimension Permutations - IEEE Journals & Magazine In this paper, we present a systematic approach to design hardware circuits for bit-dimension permutations. The proposed approach is based on decomposing a
The paper "Optimization problem formulation for semi-digital FIR digital-to-analog converter considering coefficients precision and analog metrics" by M. Reza Sadeghifar, Oscar Gustafsson, and J. Jacob Wikner is now formally published and available for download.
27/11/2018
If you happen to pass by Ajou University today. Welcome!
12/11/2018
The paper "Optimization Problem Formulation for Semi-Digital FIR Digital-to-Analog Converter Considering Coefficients Precision and Analog Metrics" by M. Reza Sadeghifar, Oscar Gustafsson, and J. Jacob Wikner has been accepted to Analog Integrated Circuits and Signal Processing.
18/07/2018
The paper "Obtaining Minimum Depth Sum of Products from Multiple Constant Multiplication" by Narges Mohammadi Sarband, Oscar Gustafsson, and Mario Garrido was accepted to the IEEE Workshop on Signal Processing Systems (SiPS). This is Narges first publication, so a special congratulations to her!
11/07/2018
Two papers accepted to Asilomar Conference on Signals, Systems, and Computers:
Erik Bertilsson, Oscar Gustafsson, and Erik G. Larsson, "A Modular Base Station Architecture for Massive MIMO with Antenna and User Scalability per Processing Node"
Madhur Gokhale, Cheolyong Bae, Oscar Gustafsson, and Mario Garrido, "Improved Implementation Approaches for 512-tap 60 GSa/s Chromatic Dispersion FIR Filters"
04/07/2018
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28/06/2018
The paper "Karatsuba with rectangular multipliers for FPGAs" by Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf won the best paper award at the IEEE Symposium on Computer Arithmetic!
The paper "SFF - The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture" by Carl Ingemarsson and Oscar Gustafsson was accepted to the special issue on Fast Fourier transform (FFT) hardware implementations of the Journal of Signal Processing Systems.
The paper shows that it is actually possible to further improve the impressive results on FFT implementation on FPGA from the earlier published, highly downloaded, paper "Efficient FPGA-Mapping of Pipeline SDF FFT Cores".
The paper "Karatsuba with Rectangular Multipliers for FPGAs" by Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf was accepted to the IEEE Symposium on Computer Arithmetic, ARITH25.
The paper is a joint effort between German, Swedish, and French researchers and shows how the multiplication complexity for long word length multiplication can be reduced when using the rectangular multipliers present in Xilinx FPGAs.
21/03/2018
In the newly released book "Arithmetic Circuits for DSP Applications" from IEEE Press/Wiley, Oscar Gustafsson and Lars Wanhammar have authored a chapter and Oscar has co-authored another.