Cister Research Centre in Realtime and Embedded Computing Systems

RTNS 2024 was a success and we would therefore like to thank all the participants who contributed to this milestone in the field of Real-Time Networks and Systems. 👏✔️

The conference photo album is now available for everyone to see.
Link to the RTNS 2024 album: https://photos.app.goo.gl/XSD2SUo43PUjHcU58

It was a pleasure to welcome participants from all continents and we hope to be able to count on you at future events.

RTNS 2024 512 new items · Album by Henrique Queirós

🚨 🚨 RTNS 2024 is just around the corner, but registration is still open.

Don't miss the chance to take part in this exciting event and discover the latest developments on the subject of Real-Time Networks and Systems.

📑 Check out the full programme for the 32nd International Conference on Real-Time Networks and Systems (RTNS 2024) here: www.cister-labs.pt/rtns24/prog

There will be an exciting keynote by Silviu S. Craciunas (TTTech, www.cister-labs.pt/rtns24/prog_keynote) and an excellent line-up of technical presentations over 3 days and 8 sessions.

Also, be sure to attend the Junior Researchers Workshop on Real-Time Computing (JRWRTC, www.cister-labs.pt/rtns24/jrwrtc).

We look forward to seeing you in Porto from 6 to 8 November 2024. Register here: www.cister-labs.pt/rtns24/reg

CISTER researchers won the Best Paper Candidate Award at RTCSA 2024.

The paper entitled "Improved Memory Contention Analysis for the 3-Phase Task Model" authored by Jatin Arora, Syed Aftab Rashid, Geoffrey Nelissen, Claudio Maia, and Eduardo Tovar was the Best Paper Candidate of the 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Application (RTCSA). RTCSA 2024 took place on 21-23 August 2024 in Sokcho, South Korea.

The paper addresses the problem of DRAM contention in modern COTS multicore platforms and provides a fine-grained analysis to upper-bound the contention that phased tasks, e.g., the 3-phase tasks, can suffer.

This achievement marks an important milestone toward predictable multicore platforms ✔

Paper Link: www.cister.isep.ipp.pt/docs/improved_memory_contention_analysis_for_the_3_phase_task_model/1900/

Distinguished Seminar - "Learn to Achieve Fast and Accurate Thermal Simulations of Multicore Microprocessors Guided by Physical Principles with Application to Thermal-aware Scheduling".
Presented by Dr. Ming-Cheng Cheng.

🎓 Next Thursday, July 25th, the CISTER member Ishfaq Hussain will defend his Ph.D. thesis entitled "Improving the analysis techniques for mixed-criticality multicore systems and controller area networks by leveraging periodic load patterns", as part of the Doctoral Programme in Electrical and Computer Engineering at the Faculty of Engineering of the University of Porto.

The jury will be composed of:

- Professor José Nuno Moura Marques Fidalgo, Associate Professor at the Faculty of Engineering of the University of Porto (President of the jury).
- Prof. Rodolfo Pellizzoni, Associate Professor of the Electrical and Computer Engineering Department of the University of Waterloo, Canada;
- Prof. Gerhard Fohler, Full Professor of the Department of Electrical and Computer Engineering of the University of Kaiserslautern, Denmark;
- Dr. Muhammad Ali Awan, Senior Engineer at Airbus Defense and Space (Advisor);
- Prof. Mário Jorge Rodrigues de Sousa, Assistant Professor of the Department of Electrical and Computer Engineering of the Faculty of Engineering of the University of Porto.

The advisory committee will be composed of:

- Dr. Muhammad Ali Awan, Senior Engineer at Airbus Defense and Space, UK;
- Prof. Pedro Alexandre Guimarães Lobo Ferreira Souto, Assistant Professor Department of informatics engineering, University of Porto, Portugal;
- Dr. Konstantinos Bletsas, Senior Researcher, CISTER research center, Porto, Portugal.

Ishfaq joined the CISTER Research Centre in 2018 and has since been developing his PhD thesis with the support of CISTER. His area of specialization is energy/performance optimization in reconfigurable MPSoC architectures.

We wish him the best of luck. 🤞

🎓 On June 25th, Yilian Ribot González successfully defended her Ph.D. thesis, supervised by Dr. Eduardo Tovar, and co-supervised by Dr. Geoffrey Nelissen and Dr. Luis Almeida, at the Faculty of Engineering of the University of Porto, Portugal.

Developed with CISTER support, her thesis entitled "Predictable Network on Chip for Real-Time Systems" proposes a set of novel NoC architectures that address performance concerns while providing deterministic timing behaviors and flexibility for various platforms and application requirements.

With this excellent milestone, we continue to fulfil our mission of helping our doctoral students to carry out their studies with excellence. ✔👏

Read the full article: www.cister-labs.pt/news/972

📢 CISTER IS OPENING A NEW CALL FOR PH.D. STUDENTS ❗️

◾️ What are we looking for?

CISTER is currently soliciting applications from enthusiastic individuals for its Graduate Research Program, which offers opportunities in the following areas: (1) Embedded and Real-Time Computing Systems, (2) Cyber-Physical Systems, (3) Internet of Things, and (4) Mobility and related technologies.

◾️ What do we offer?

CISTER offers research fellowships for a period of up to four years with a salary of between € 13,000.00 and € 15,000.00 (after tax) per year as well as payment of tuition fees (€ 3500.00 per year). A research stay at CISTER offers the opportunity to become part of national and international networks of researchers and companies in an exceptional, dynamic, multicultural and stimulating research environment.

More information about the application and how to apply:
www.cister-labs.pt/jobs/348/call_for_expressions_of_interest_in_phd_studies/

Deadline for applications: July 4th, 2024.

Don't miss this opportunity to work in a world-leading research unit in the fields of Real-Time Embedded Computing Systems (RTECS) and Cyber-Physical Systems (CPS) with researchers from more than 20 countries and more than 300 international international partners from academia and industry.

On June 27, we will host a Distinguished Seminar, entitled “Learn to Achieve Fast and Accurate Thermal Simulations of Multicore Microprocessors Guided by Physical Principles with Application to Thermal-aware Scheduling”, presented by Dr. Ming-Cheng Cheng.

Ming-Cheng Cheng received the B.S. degree in Electrophysics from National Chiao-Tung University, Taiwan, and the Ph.D. degree in Electrical Engineering from Polytechnic University, Brooklyn, NY, USA. He is currently a professor in Electrical and Computer Engineering at Clarkson University, Potsdam, NY.

His research has covered a wide range of areas including electron transport modeling of solid-state devices, spin-polarized electron transport, electro-thermal simulations of semiconductor devices and integrated circuits, electromagnetic simulation for core losses in magnetic materials. Recently, he has devoted his effort to developing effective physics simulation methods based on physics-informed data-driven learning algorithms for different research areas, including dynamic thermal analysis of ICs, CPUs/GPUs, thermal-aware task scheduling in multi-core microprocessors, simulations of quantum eigenvalue problems for nanostructures and materials, DFT simulations, electromagnetic/photonic simulations, etc.

Make sure you book the slot in your agenda! ✔️

For more information: www.cister-labs.pt/events/ming_cheng_cheng/

Distinguished Seminar - “Data Flow from Cause to Effect in Distributed Systems: Data Age and Reaction"
Presented by Dr. Jian-Jia Chen

Distinguished Seminar - “Differentiating with Custom Computing and RISC-V”
Presented by Dr. Pavel Zaykov

🎓 On April 26th, Javier Pérez Rodríguez successfully defended his PhD thesis, supervised by Dr. Patrick Yomsi, and co-supervised by Dr. Eduardo Tovar and Dr. Luis Almeida, at the Faculty of Engineering of the University of Porto.

Developed with CISTER support, his thesis entitled "Thermal-aware schedulability analysis for modern real-time computing systems" addresses the challenge of managing heat dissipation in computing systems, particularly in safety-critical domains. It proposes novel thermal-aware resource management schemes for multi-core platforms to meet real-time requirements without exceeding thermal limits.

With this great achievement, Javier kicks off this year's series of PhD thesis defenses by CISTER members in the best possible way. ✔👏

Read the full article: www.cister-labs.pt/news/969

🎓 Next Friday, April 26th, the CISTER member Javier Pérez Rodríguez will present his PhD thesis entitled "Thermal-aware Schedulability Analysis for Modern Real-time Computing Systems", as part of the Doctoral Programme in Electrical and Computer Engineering at the Faculty of Engineering of the University of Porto.

The jury will be composed of the following members:

Dr. José Nuno Moura Marques Fidalgo, Associate Professor, Faculty of Engineering, University of Porto (President);
Dr. Jian-Jia Chen, Professor at the Department of Computer Science at TU Dortmund University, Germany;
Dr. Sandro Emanuel Salgado Pinto, Principal Researcher at the ALGORITMI Centre at the University of Minho;
Dr. Pavel Zaykov, Lead Innovation & Research Engineer at Codasip Labs;
Dr. João Paulo de Castro Canas Ferreira, Associate Professor, Department of Electrical and Computer Engineering, Faculty of Engineering, University of Porto;
Dr. Patrick Meumeu Yomsi, Researcher at CISTER - Centre for Research in Embedded Computing Systems and Real-Time at the Porto Higher Institute of Engineering (Supervisor).

Javier joined the CISTER Research Centre in 2018 and has since been developing his PhD thesis with the support of CISTER. He was also holder of an FCT individual grant.

We wish him the best of luck. 🤞



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