23/09/2026
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๐ซ๐จ๐ฆ ๐๐๐๐ ๐๐๐๐ ๐ญ๐จ ๐๐๐๐-๐ ๐๐ฎ๐ฆ๐ฆ๐ข๐ญ ๐๐ก๐ข๐ง๐ ๐๐๐๐
๐๐ฎ๐ซ ๐๐-๐๐ฉ๐๐ซ๐ฌ๐ ๐๐๐๐๐ฉ๐ญ๐๐ ๐๐ญ ๐๐๐๐-๐ ๐๐ฎ๐ฆ๐ฆ๐ข๐ญ ๐๐ก๐ข๐ง๐ ๐๐๐๐!
We are excited to share that our research proposal โRV-Sparse: RISC-V Vector Acceleration for Sparse General Matrix-Matrix Multiplication" developed at the Micro Electronics Research Lab (MERL), UIT University has been accepted for presentation at RISC-V Summit China 2026.
The work focuses on leveraging RISC-V vector architecture to accelerate sparse matrix computations, with the goal of improving performance for emerging high-performance computing and AI workloads.
We are Grateful to everyone who contributed to and supported this work. Looking forward to sharing our research with the RISC-V community in China!