SVM Micro Systems

24/09/2015

Training in VLSI Front End Design & Verification :

We offer Job Oriented training in VLSI FRONT END DESIGN & VERIFICATION.
This course mainly concentrates on all the prerequisites that you need to get a job in VLSI DESIGN & VERIFICATION.

Training Modules : "Verilog HDL", "System Verilog HVL", "UVM".

Highlights :
Expert Faculty,
Updated Methodologies,
Example Projects,
Mock Interviews,
Interview Faq Discussions.
Placement assistance *

We also offer B.tech/M.tech Academic Projects.You can Request the List of Projects from Here

https://docs.google.com/forms/d/1n8YJEf8m6mdRi3akhzUb71YgzLLEtmNQ2lWRkkHVpOE/viewform?edit_requested=true

NEW BATCH STARTS ON 03/10/15.

To register, you can drop your details here.

https://docs.google.com/forms/d/1OcDuBes0ERwHX5LSFi9NvBAqNiMgr7udBxJCMbYUPDs/viewform?usp=send_form

Please get back to us for any kind of queries.

24/09/2015

Looking for B.tech / M.tech academic Projects..?
You can request us for the List of projects here.

https://docs.google.com/forms/d/1n8YJEf8m6mdRi3akhzUb71YgzLLEtmNQ2lWRkkHVpOE/edit #

05/09/2015

Happy Teacher's Day :-)

24/07/2015

14/05/2015

Verilog HDL

At SVM Micro Systems, This Saturday(16/5/15) there is a new Batch starting for VERILOG HDL.

About this Verilog HDL Course :
-- Classes will be delivered by Working professionals from an MNC in hyd, having 3+ years of experience in VLSI DESIGN & VERIFICATION.
-- Duration : 25 - 30 days;
-- WEEKDAY BATCHES - (5 days a week),
-- WEEKEND BATCHES.
-- Interview faq discussions
-- Practice assignments/projects
-- FEE : 4000 rs (only for verilog hdl)

if some one is interested , You may come to us for a demo class .

please get back to us for any queries/other module's / or demo class timings.

--
SVM MICRO SYSTEMS

10/05/2015

29/04/2015

UVM classes start's this saturday (02/05/15).
Duration : 1 Month
timings : 7:30 am to 8:30 am or
7:00 pm to 8:00 pm.
Course Fee : 12000 rs /-

17/04/2015

Demo class on "UVM"

16/03/2015

Hardware Description Verification Language (System Verilog) and Universal Verification Methodology(UVM) classes will starts from 23rd-March-15(New Batch:03) . Enroll ASAP .

Please contact for new batch in weekend +91-7093 04466 ;
Email-id: [email protected]
https://twitter.com/SVMMicroSystems

https://twitter.com/SVMMicroSystems/status/577518415000158208

27/02/2015

Hardware Verification Language (System Verilog) classes started from 23rd-FEB-2015. Enroll ASAP
Please contact for new batch in weekend +91-7093 04466 ;
Email-id: [email protected]
https://twitter.com/SVMMicroSystems

06/01/2015

https://www.facebook.com/SVMMicroSystems

https://twitter.com/SVMMicroSystems

Greetings from SVM Micro Systems ..
Advanced VLSI Training now in HYD @ SVM Micro Systems.

We are offering 'VLSI Front End Design and Verification" courses for B.Tech (ECE/ EIE/EEE) , M.Tech(VLSI) students and VLSI professionals. This course is designed by our faculty, having high VLSI industrial & training experience.


Courses offered.
Advanced Digital Design & Verilog
System Verilog
UVM
Unix, Perl, C-Shell
Projects on System Verilog and UVM
Exposure on Protocols like AHB,APB,I2C,I2S,SPI ..etc
Our students will have enough hands-on experience that they can be compared to one to two year industry experience individuals after completion of course.

We give placement assistance on successful completion of the course

Hurry Up ..!

To enroll , please contact us.

Please go through the attached Document for complete Course Schedule.

With Best regards:
SVM Micro Systems,
KPHB, Kukatpally,
+91 7093704466
040 40064677

To make students ready for the industries.

04/01/2015

Verilog HDL Language Classes starts from 5th-Jan-2015 , 7:00 AM to 8:30 AM. Enroll ASAP
https://twitter.com/SVMMicroSystems/status/551786667325935616/photo/1