VLSI Final Year Projects for M.Tech and B.E in Greater Noida Gurgaon Delhi

22/07/2016

Any one interested in the implementation of following ieee paper on MATLAB
"A DWT-DCT-SVD Based Digital Image Watermarking
Scheme Using Particle Swarm Optimization"
Abstract—In this paper, we propose a hybrid watermarking
scheme for digital images based on singular value decomposition
(SVD) and particle swarm optimization (PSO). The two key
aspects of watermarking schemes are copyright protected and
robustness. In this, we are embedded the principal components of
the watermark in the DCT domain of DWT subband of host
image, for providing copyright protection as well as reliability.
Since Scaling factor is an image dependent so we are providing it
in the form of a matrix. PSO is used for finding suitable scaling
factors such that to provide efficient robustness and fidelity of the
scheme. Experimental results are provided to illustrate that the
proposed scheme is able to withstand a variety of image processing attacks as well as imperceptibility.

you can see slides also on this paper. click over the link
http://www.slideshare.net/vikasgarg313/watermarking-64272618

30/03/2016

Hi friends,
I am going to conduct weekend classes & training program related to your course with full day practical learning classes.
Fields covered in this training:
Basics of Electronics for 1st year students (Duration~35 hours)
Digital Electronics for 2nd Year CSE/ECE/EEE students (Duration~35 Hours)
Digital System Design For CSE/ ECE 6th Sem Students (Duration~30 Hours)
Control System for ECE 6th Sem students (Duration~35 Hours)
Basics of Matlab for all branches of all years (Duration~30 Hours)
Linux For CSE/ ECE (3rd & 4th) year Students (Duration~24 Hours)
Verilog For ECE (3rd & 4th) year Students (Duration~30 Hours)
VHDL For ECE (3rd & 4th) year Students (Duration~30 Hours)
Interested students can contact me on 9711759682 or [email protected]. You can also refer this to your friends
Venue for classes: Faridabad

25/03/2016

Verilog Course Details:(Aprox~40 hours)
Introduction
Modeling styles and Gate Level Modeling
Verilog Conventions and Test Bench Writing
Data Types
Data Flow Modeling and Operators
Behavioral Modeling
Advanced Verilog
Digital Design Course Details:(Aprox~30 hours)
Basics of Digital Design
Understanding Combinational Logic/Circuit Designing
Understanding Sequential Logic/Circuit Designing
Digital Design Flow Modeling
Advanced Digital Design
Exercises

25/03/2016

For Interested students, I am going to conduct summer training program on weekends with full day practical learning classes related to students interest. Fields covered in this training: Matlab, VLSI (Linux, Digital design, verilog, vhdl, and advanced digital design using verilog.
Duration : April- July
Projects: according to students requirements
For more info, you can contact on 9711759682

08/04/2015

Free Professional 6 weeks Mentor Graphics System Verilog Training program for B.Tech & M.Tech students : June 15 - July 31, 2015

“Verification of Electronic Design and Systems using SystemVerilog” for students. The course will be for 6 weeks and it will include projects and extensive labs using Mentor Tools. This is a free program for candidates selected through Mentor Graphics all India selection program.

http://www.mentor.com/india/india-sv-training

08/04/2015

https://docs.google.com/forms/d/11vQB5hFKXCrnA0aqQMnWACEIuJ2sL8gZJtJxFcsEk_8/viewform?c=0&w=1

Cadence Design Systems seeks applications for internship in analog physical design from B.E/B.tech holders (who are in Final year or already passed out or). The selected candidates will go through a 6-month internship program. During that period they will be trained extensively in the field of Analo…

07/04/2015

SION is hiring 0-2 Yrs VLSI engineers in Physical Design & Layout : 25 Openings
SION Semiconductors Private Limited, is planning to hire passionate M.Tech / B.Tech graduates (0-2yrs experience) for clients requirements.
Requirements:
1) M.Tech / B.Tech in Electronics, with minimum aggregate of 60%, and 2013, 2014 and 2015 passouts from reputed engineering colleges
2) Must have got trained in any reputed training center in Layout and Physical Design
3) Must be very good at Digital design basics
4) Very good at analytical and logical reasoning
This would be wonderful opportunity for candidates waiting to enter into VLSI Industry. Interested candidates can send their resumes to [email protected]
Only short-listed candidates will be called for written test followed by personal interview