DESE IISc Bangalore

DESE is organising 5-day workshop on "Course Design in OBE & NBA Framework” only for 40 participants. Kindly register to attend.

Apply for our MTech EPD program

Join us on 24th Feb

DESE welcomes new assistant professor Dr Debayan Das from Intel Hillsboro. Dr. Das’s research focuses on Analog/Mixed signal IC design, Hardware security and internet of bodies.

Explore, connect and execute with us on 4th March

DESE is proud to announce that all second year students of our three MTech programs: MVLSI, ESE and EPD got placed in companies like Samsung, TI, Analog Devices, Qualcomm, Intel etc. within 1.2 years of their admissions. In present situation this is really something to brag on. Semiconductor-VLSI-Electronics is recession-proof!

Congratulations to Utsav Banerjee on being the 2022 recipient of the ABB Research Award to continue his research on innovative integrated circuits and systems for increased security of connected devices in the Internet of Things. This is one of the most highly endowed global research awards given by a corporation, and is awarded every three years to an early-career academic researcher from among several international applicants through a highly competitive selection process.

2022 ABB Research Award in Honor of Hubertus von Grünberg ABB awards $ 300,000 grant over the next three years to Utsav Banerjee for on-going research that will improve security with connected devices.

DESE Students from Reconfigurable Computing Lab has received the Nripendra Nath Biswas Best Student Paper Award in International Conference on VLSI Design (2022) for designing a Hardware Accelerator for Capsule Network based Reinforcement Learning.

Hardware Accelerator for Capsule Network based Reinforcement Learning Convolutional neural networks are widely used in reinforcement learning. Capsule networks are gaining popularity over the traditional convolutional neural networks in many classification tasks. A capsule is a multidimensional activity vector consisting of neurons that represent the features of a spe...

Reconfigurable Computing Lab, DESE, has designed a RISC-V Vector Processor for Edge-AI applications. RISC-V Vector processor shows a speedup of up to 40.7x over the scalar RISC-V core on image recognition tasks at the cost of 1.2x power consumption and 1.8x hardware resources.

A Soft RISC-V Vector Processor for Edge-AI Edge computing is the key to unlocking the power of deep neural networks on edge devices. However, deploying power-hungry deep neural network inference on resource-constrained and power-limited devices poses serious challenges in delivering real-time performance. With the advent of RISC-V Vector ext...

Ganesh Chaturthi @ DESE

Department of Electronic Systems Engineering (DESE), EECS, IISc has shared two Softcore Processor IPs developed at DESE. These are developed by the Reconfigurable Computing Lab of DESE. First one is a 32-bit RISC-V Processor, and the second a 32-bit RISC-V Vector Processor. These are targeted to FPGAs and can be modified for ASIC implementation. The link for these IP's are below:
https://labs.dese.iisc.ac.in/rclab/resources/

Resources | Reconfigurable Computing Lab

DESE welcomes its new assistant professor Dr. Viveka KR, who will be working in the area of memory design, in-memory computing, human-machine interface, and secure computing.

Second session of AIM 2022.
Whoever has missed the first session please join us on 18th March at 6PM

Friday 5:30 PM IST. Do join us.

DESE offers country’s best MTech programs in electronics. If you are exited about electronics do apply for our MTech programs.

Researchers from the Department of Electronic Systems Engineering report a fully automated computational framework that can assess the energy storage capacity of thousands of 2D materials in a high-throughput fashion.

https://iisc.ac.in/computational-pipeline-to-search-for-2d-energy-storage-materials/

Best poster award - 14th International Conference on COMmunication Systems & NETworks, IEEE COMSNETS 2022 (attached)

In this work, DESE researchers have designed and implemented the IEEE 802.15.4e-TSCH protocol using GNU radio systems. The goal was to create a user-configurable tool to test several future applications that might use deterministic MAC protocol.
The main blocks that were implemented include: (a) Clear Channel Assessment using energy thresholding (b) Frequency and Channel hopping (c) All Frame structures.

Congratulations to Prashant Surana, Syam Sundar Nair and Subhabrata Basak from Power-electronics lab, Sreenivas Bhaskara from Biomedical and Electronic Engineering Systems Laboratory,
Harsh Raj, MSD Lab
Ankita Nandi, NeuRonICS Lab
Banhimitra Kundu NeuRonICS Lab for having qualified for the prestigious PMRF scholarship.

DESE welcomes its new assistant professor Dr Utsav Banerjee. Dr Banerjee, did his PhD from Massachusetts Institute of Technology and works in the domain of cryptography and hardware security.

Mid-year PhD admission portal is now open. Application deadline: 31st October 2021. Interview will be conducted online in the last week of November.
https://www.iisc.ac.in/wp-content/uploads/2021/09/detailed-mid-year-admission-advertisement-2021.pdf

www.iisc.ac.in

Telecom operators are always interested in minimizing network design cost. We formulate an optimal network design problem taking both server location and link capacity costs into account. The search space in the resulting Integer Linear Program is huge. We apply the Column Generation technique to provide an exact solution in very reasonable time. Results show a 40% improvement in design cost, compared to heuristic solutions.

https://ieeexplore.ieee.org/document/9463681

Service Scheduling for Random Requests With Deadlines and Linear Waiting Costs We study service scheduling problems in a slotted system where jobs arrive according to a Bernoulli process and leave within two slots after arrival. Service costs are quadratic in service rates, and there is also a linear waiting cost. We frame the problems as average cost Markov decision processes...

GATE: What, Why and What After?
Thursday, September 30 · 12:00 – 1:00pm
Google Meet joining info
Video call link: https://meet.google.com/htb-fnuh-zxx

Flyer of new MTech program in Electronic Product Design (EPD). Online portal is now open for application.

M.Tech programme in Electronic Product Design (EPD) at IISc Bangalore
https://www.iisc.ac.in/admissions/

Indian Institute of Science Bangalore IISc is the premier institute for advanced scientific and technological research and education in India.

Researchers from the Reconfigurable Computing Lab of the Department of Electronic Systems Engineering developed a hardware accelerator for the Hoeffding tree algorithm with adaptive naive Bayes predictor in the leaves. The proposed system can accelerate data streams with both nominal and numeric attributes using minimum hardware resources for large datasets.
https://ieeexplore.ieee.org/document/9418100

High Throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. The algorithm involves complex time consuming computations in the leaves of the tree for each data instance. These computations involve a lot of parallelisms which can be exploited and im...