10/08/2023
Hiring alert🔊
New job openings at Maverick Semiconductor
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https://www.linkedin.com/posts/maverick-semiconductor_maverick-semiconductor-and-services-is-hiring-activity-7074700540076556288-xmda?utm_source=share&utm_medium=member_desktop
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Maverick Semiconductor and Services on LinkedIn: Maverick Semiconductor and Services is hiring for Design and verification… | 19 comments
Maverick Semiconductor and Services is hiring for Design and verification Engineers for Bangalore, Noida, Chennai, and Pune location with 0-5 years of… | 19 comments on LinkedIn
26/07/2023
Check out these most asked System Verilog interview questions, kindly go through these questions if you are applying or preparing for interview:
1. What is constraint solve-before?
2. What is coverage and what are different types?
3. What is the importance of coverage in SystemVerilog verification?
4. When you will say that verification is completed?
5. What are illegal bins? Is it good to use it and why?
6. What is the advantage of seed in randomization?
7. What is circular dependency?
8. What is “super “?
9. What is the input skew and output skew in the clocking block?
10. What is a static variable?
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14/07/2023
Check out these most asked SV & UVM interview questions, kindly go through these questions if you are applying or preparing for interview:
1. Have you ever developed SV test-bench explain in brief?
2. What is the difference between pass by ref and pass by value?
3. Explain arguments using ref keyword and without using it?
4. Have you ever used const keyword in constraints give one example of it.
5. If the functional coverage is 100% and code coverage is not 100% what does that mean?
6. What is UVM factory? What is the use of factory?
7. Explain the flow in uvm components?
8. What is factory registration and what is the use of registering components in the factory?
9. What are UVM Phases and why are they created, what is the use of them?
10. Where is the connection between monitor and scoreboard?
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26/06/2023
Check out these most asked System Verilog interview questions, kindly go through these questions if you are applying or preparing for interview:
1. What are the different layers of layered architecture?
2. What is the difference between a $rose and @ (posedge)?
3. What is the use of extern?
4. What is scope randomization?
5. What is the difference between blocking and non-blocking assignments?
6. What are automatic variables?
7. What is the scope of local and private variables?
8. How to check if any bit of the expression is X or Z?
9. What is the Difference between param and typedef?
10. What is `timescale?
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09/06/2023
Check out these most asked SV & UVM interview questions, kindly go through these questions if you are applying or preparing for interview:
1. What is the difference between logic and wire data types?
2. How to define a queue (syntax)?
3. Can we fix size of queue?
4. What is the difference between shallow copy and deep copy?
5. What is polymorphism and why is it used?
6. How the communication between the components is taking place in System Verilog?
7. Explain the concept of semaphore and its use? Different methods used?
8. What is the difference between virtual and pure virtual functions?
9. What are different types of code coverage?
10. How we connect dut and test bench using interface?
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29/05/2023
Check out these most asked UART interview questions, kindly go through these questions if you are applying or preparing for interview:
1. What is UART and the purpose of UART ?
2. How UART protocol work ?
3. How do you communicate with UART?
4. Is UART Synchronous or Asynchronous
5. Why USART used?
6. What is the best Baud rate to use?
7. Why do we use Baud concept & how do we achieve Baud rate?
8. Difference between Bit rate & Baud rate.
9. What is the importance of strobe & cycle?
10. What is the standard speed of UART?
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01/03/2023
Hiring alert🔊
New job opening at Excelmax.
Hurry up and apply now!
https://www.linkedin.com/posts/suman-ragotham-1a387b1_jayaprakash-yangalnihar-shettysathish-shanmugam-activity-7031504718501736450-Ow4B?utm_source=share&utm_medium=member_desktop
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28/02/2023
Check out these most asked AHB Protocol interview questions, kindly go through these questions if you are applying or preparing for interview:
1. How AHB is pipelined Architecture?
2. The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?
3. Why is a burst not allowed to cross a 1-kilobyte boundary?
4. Can an AHB master be connected directly to an AHB slave?
5. What is the state of the AHB signals during the reset?
6. Can a BUSY transfer occur at the end of a burst?
7. What is a default slave?
8. Is a default slave really necessary?
9. Is a dummy master really necessary?
10. Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?
11. What default state should be used for the HREADY and HRESP outputs from a
slave?
12. Is HREADY an input or an output from slaves?
13. How many masters can there be in an AHB system?
14. Can a master change the address/control signals during a waited transfer?
15. When a master rebuilds a burst which has been terminated early are there any
limitations on how it rebuilds the burst?
16. What is the recommended default value for HPROT?
17. Do all slaves have to support the BUSY transfer type?
18. What system support is required if a slave can be powered down or have its clock
stopped?
19. When can Early Burst Termination occur?
20. Does the address have to be aligned, even for IDLE transfers?
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VLSI Job Aspirants😎✌️🎓
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24/07/2023
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