Abhiyantha

Looking to get started with ASIC Design & Verification?

Join our live session Webinar covering the complete RTL-to-Netlist flow, including:
✔ Verilog coding
✔ Simulation & testbench
✔ Coverage & formal verification
✔ Synthesis & LEC

📅 May 08, 2026
⏰ 1:30 PM – 4:00 PM

🎯 Tools: Cadence Xcelium, IMC, JasperGold, Genus & more

Great for students and professionals in electronics & VLSI.

👉 Register today – limited seats available - https://www.abhiyantha.com/trainings/registration/vlsi-utb?src=web&p=utb

Join our Part 2 session on Designing & Implementing a Half-Adder using Cadence Tools and learn how real chip layouts are built and verified 💡

📅 April 24th, 2026
⏰ 1:30 PM – 4:00 PM

💡 Session Highlights:
✅ Layout design of basic gates (XOR, AND, Inverter)
✅ Half-Adder layout implementation
✅ Physical verification & parasitic extraction
✅ Post-layout simulation & GDSII extraction

Don’t miss this learning experience!

Register now: https://www.abhiyantha.com/trainings/registration/vlsi-utb?src=web&p=utb

🔔 FREE Webinar | ASIC Physical Design & Verification (RTL-to-GDSII)

Hey everyone! Incase you missed last week's Live Session, We're again back with Part 2 of our ASIC Design series — Recorded Session

If you attended Part 1 on Front-End Design, you know what to expect. If you didn't — no worries, we'll recap the first 30 mins!

📋 What we'll cover:
• Netlist preparation for Physical Design
• Floor & Power Planning
• Placement, CTS & Routing
• Timing & Power Analysis
• Post-layout Simulation & Logic Equivalence Check
• GDSII Tape-out

🛠 Tools: Innovus · Quantus · Voltus · Conformal LEC · Xcelium
📅 Wednesday, Mar 25 | 6:00 PM – 8:00 PM IST
💻 Online | FREE

📅 Friday, Mar 27 | 1:30 PM – 4:00 PM IST
💻 Online | FREE

👉 Register: https://www.abhiyantha.com/trainings/registration/vlsi-utb?src=web&p=utb

Share with your VLSI/ECE friends! 🙌

🌙📘 May this Eid bring knowledge, growth, and new opportunities for learning and success.
Wishing everyone a blessed and joyful Eid.

Eid Mubarak from Team Abhiyantha.

🚀 LIVE VLSI SESSION – PART 2
ASIC Design & Verification of 8:3 Encoder (RTL-to-Netlist)

📅 Mar 20, 2026
⏰ 1:30 PM – 4:00 PM

Learn the complete ASIC Physical Design Flow step-by-step:
⚡ Floorplanning
⚡ Placement & CTS
⚡ Routing
⚡ Timing & Power Analysis
⚡ Post-layout Simulation
⚡ GDSII Generation

🛠 Tools Used:
Innovus | Quantus | Voltus | Conformal LEC | Xcelium

🎯 Must attend for VLSI / ECE / EEE / Engineering students

🔥 Limited seats — Register now - https://www.abhiyantha.com/trainings/registration/vlsi-utb?src=web&p=utb

VLSI Analog Layout – Online Training Program

📘 What You Get
✅ Core Analog Layout concepts & industry tools
✅ Live online sessions led by expert mentors
✅ Structured learning with design exposure

🎯 Who Should Join?
✔️ Students | Graduates | Research Scholars | Professors | Working Professionals

🗓 Start Date: 18th March, 2026
🖥 Mode: Online
⏰ Timing: 6:30 – 8:30 PM (Evenings)
📅 Schedule: Every Wednesdays, Fridays & Saturdays
⏳ Duration: 3 Months

👉 Apply Now:
https://www.abhiyantha.com/skill-development-program/vlsi-analog-layout

🟩 Join WhatsApp Channel:
https://whatsapp.com/channel/0029Vb5ZuKf002T8cFcMVD2M

📞 9353901711
📧 [email protected]
🌐 www.abhiyantha.com

⚡VLSI SESSION – CADENCE TRAINING ⚡

Single Stage Common Source Amplifier using Cadence EDA Tools

📅 Mar 13
⏰ 1:30 – 4 PM
🎥 Recorded session

Learn:
✔ NMOS Amplifier
✔ Cadence Virtuoso
✔ Spectre Simulation
✔ Layout Design
✔ Assura / PVS
✔ Post-Layout Simulation

🎯 For ECE / EEE / VLSI Students

Seats Limited ⚠

Register Now: https://www.abhiyantha.com/trainings/registration/vlsi-utb?src=web&p=utb

Digital design focuses on logic and scalability.

Analog layout focuses on precision and performance.

In advanced semiconductor technologies, layout directly influences circuit behavior — through device matching, parasitic control, symmetry, and layout-dependent effects.

If you're serious about understanding how real silicon works, this blog is for you:

📘 Analog vs. Digital VLSI Layout: Why Analog Skills Give You an Edge

Read here:
🔗 https://www.abhiyantha.com/blogs/analog-vs-digital-vlsi-layout-why-analog-skills-give-you-an-edge

🚀 Our Analog Layout Skill Development Program starts March 4.
Use code MKTG24 for a limited-time discount.