28/12/2025
Creating an MCU (Microcontroller Unit) from an FPGA is done by implementing what is called a Soft Processor Core. Instead of a physical silicon chip, you use the FPGA's logic resources (LUTs, Flip-Flops, RAM) to build a functional CPU and connect it to peripherals.
Here is the step-by-step workflow to turn your FPGA into a functioning MCU.
The Concept: "Soft Core" vs. "Hard Core"
Soft Core: A CPU described in code (Verilog/VHDL) that you "load" into the FPGA fabric. It is flexible but slower (e.g., MicroBlaze, Nios II, RISC-V). This effectively "makes" an MCU out of the FPGA.
Hard Core: Some FPGAs (SoCs like Zynq or Cyclone V) come with a physical ARM processor already on the silicon. This is not "made" from the FPGA fabric; it sits alongside it.
Phase 1: The Hardware Design (Building the "Chassis")
This phase defines the architecture of your custom MCU using the FPGA vendor's tools.
1. Choose Your Processor Core
Vendor Specific: Optimized for their chips but proprietary.
Xilinx (AMD): MicroBlaze (32-bit RISC).
Intel (Altera): Nios II or Nios V (RISC-V based).
Open Source: Portable across any FPGA.
RISC-V: Highly popular, free (e.g., NEORV32, PicoRV32).
PicoBlaze: Very tiny 8-bit controller for simple state machines.
2. Configure the System (Block Design)
You don't usually write Verilog for the CPU itself; you use a Block Design tool (like Vivado IP Integrator or Platform Designer).
Instantiate the Core: Drag and drop the processor IP into your design.
Add Memory: Connect the CPU to Block RAM (BRAM) for small internal memory or a DDR controller for large external RAM.
Add Peripherals: This is what makes it an MCU rather than just a CPU. Add AXI/Avalon-based IPs for:
GPIO: To read buttons and blink LEDs.
UART: For serial communication with a PC.
Timers/Interrupt Controllers.
3. Synthesis & Bitstream
Address Mapping: Assign memory addresses to your peripherals (e.g., LEDs are at address 0x4000_0000).
Generate Bitstream: Compile the hardware design into a .bit (Xilinx) or .sof (Intel) file. This file configures the FPGA to become the MCU hardware.
Phase 2: The Software Design (The "Brain")
Once the hardware is defined, you need to write the software that runs on it, just like programming an Arduino or STM32.
1. Export Hardware
Export your hardware definition (XSA for Xilinx, SOPCINFO for Intel) to the Software Development Kit (SDK).
Tools: Vitis (Xilinx), Nios II EDS (Intel).
2. Write Firmware (C/C++)
The SDK will generate a Board Support Package (BSP). This contains the drivers for the custom peripherals you added in Phase 1 (e.g., XGpio_WritePin()).
Write your main.c application code using these drivers.
3. Compile & Link
Compile your C code into an executable binary (.elf file).
Phase 3: Deployment
Program the FPGA: Load the hardware bitstream via JTAG. The FPGA is now configured as a processor.
Load the Application: Download your .elf software file into the FPGA's memory via JTAG.
Run: The soft core starts fetching instructions and executing your code.