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VHDL-2008 added a shorthand for importing the standard IEEE packages: the predefined ieee_std_context.

library ieee;
context ieee.ieee_std_context;

That one line pulls in std_logic_1164 and numeric_std, the two you use in almost every file.

Available in VHDL-2008 and onwards.

Stuck implementing a VHDL module? Here's a trick that feels like cheating.

Write a non-synthesizable behavioral version first using processes and wait statements. Get it working in the simulator, build your testbench around it, then convert it to a state machine.

For loops in VHDL can produce very different hardware. In a testbench, it iterates like a programming language. In a Gray code converter, it becomes seven parallel XOR gates. In a parity generator, it becomes a deep XOR chain that limits your maximum clock frequency.

What you put inside the loop decides what hardware you get (if any).

The full video walks through six examples in Vivado, including a For loop that synthesizes to no logic at all: https://www.youtube.com/watch?v=chexAqY0x9A

Loops are some of the most misunderstood constructs in VHDL. Sometimes they behave like loops in a regular programming language. Other times they create lots of parallel hardware, deep combinational paths, or even no logic at all.

In this video, I walk through six VHDL For loop examples and show exactly what each one synthesizes into using Xilinx Vivado. The same principles apply to While loops and basic Loop statements.

Content:

Example 1: For loop in a testbench (simulation only)
Example 2: Parallel logic (Gray code converter)
Example 3: Deep combinational logic (parity generator)
Example 4: Parallel flip-flops (register array)
Example 5: Pipeline of chained flip-flops
Example 6: A For loop that synthesizes to no logic

Want to go deeper?

The full course, VHDL synthesis: From code to hardware, walks through 20 VHDL module examples and analyzes the elaborated (RTL) and synthesized netlists for each one. The last seven of the 19 lessons focus on finite-state machines.
👉 https://vhdlwhiz.com/product/course-vhdl-synthesis-from-code-to-hardware/

The best way to get it is through the VHDLwhiz Membership, where you also get 40+ other VHDL courses and a full resource library of demo projects, scripts, and templates. New content every month, cancel anytime.
👉 https://academy.vhdlwhiz.com/membership

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Keep coding! 😎
Jonas

Should I learn VHDL or Verilog first? Here are some thoughts.

Verilog or VHDL more popular? That depends on the industry (FPGA/ASIC) and on your geographic location.

A VHDL process with a sensitivity list is equivalent to a process with a Wait On statement at the end, listing the same signals as the sensitivity list.

Learn how to build a system-on-chip (SoC) design by using a MicroBlaze soft-core processor, existing IP cores, and custom VHDL modules.

Get the course from the VHDLwhiz shop:
https://vhdlwhiz.com/product/course-microblaze-soc-design/

The most cost-effective way to develop an FPGA design is to combine software and hardware and use existing IP cores when available. You get the best of both worlds by using software to implement the control path and hardware for the data-intensive parts with strict timing requirements.

You can turn most FPGA projects into SoC designs using a soft-core processor like Xilinx’s MicroBlaze, and I will walk you through setting up such a system from scratch in this course.

I use the Digilent Arty S7 FPGA development board, but many other Xilinx boards will work too.

However, you may have to make slight modifications to the design, depending on which features exist on your board. I will mention that when we get to those parts of the course.

If you don’t have a suitable board, you can still install the software and do all exercises. I will show the results on my board anyway.