TTTC Seminar on VLSI Testing and Testability

19/06/2024

15/11/2023

Dear Sir/madam,

School of Electronics Engineering (SENSE), VIT, Vellore organizing a two-week National workshop (online) on "System On Chip Design using Open-power" from November 20, 2023 to December 2, 2023 supported by IBM, OpenPower and Object Automation.

Eminent speakers from Industry, National Laboratories and IITs will handle the session.

You are cordially invited to register and attend the workshop. Virtual lab access will be provided to all the participants.

Registration fee: Rs 2000/-
For registration, https://events.vit.ac.in/
on or before 18.11.2023

03/03/2020

TTTC Seminar on
VLSI Testing and Testability

March 13-15, 2020

Organized by
Department of Micro and Nano Electronics
School of Electronics Engineering

Vellore Institute of Technology, Vellore, Tamil Nadu– 632 014



For registration, please visit:
https://events.vit.ac.in/





Speakers

Professionals from various Semiconductor Industries sponsored by

Test Technology Technical Council (India)

(https://site.ieee.org/tttc-india/)

&

Faculty members from

Vellore Institute of Technology, Vellore

(https://vit.ac.in)

Established in 1984 VIT University is a progressive educational institution that is dedicated to the pursuit of excellence.